module mux2_1(InA,InB,S,Out);

	input InA;
	input InB;
	input S;
	output Out;

	wire S_bar;
	wire PathA;
	wire PathB;
	not1 INV0 (.in1(S),.out(S_bar));
	nand2 G0 (.in1(S_bar),.in2(InA),.out(PathA));
	nand2 G1 (.in1(S),.in2(InB),.out(PathB));
	nand2 G2 (.in1(PathA),.in2(PathB),.out(Out));

endmodule
